This invention relates to processes for making dielectrically isolated complementary bipolar devices and/or complementary MOS devices using selective epitaxial growth (SEG) techniques.
Bipolar and MOS devices in state of the art circuits are used in complementary pairs, and, in high voltage circuits, are typically combined with complementary high voltage DMOS devices in the same IC. It is important that these device species be isolated, and the fabrication sequence for the different types of devices be compatible. Various isolation techniques have been used as complementary bipolar technology has evolved. LOCOS processes were used for many years but encountered severe leakage problems as device dimensions shrunk. Trench isolation techniques with upside down wafer preparation are widely used but are cumbersome and expensive by current silicon processing standards. A more recent approach uses selective epitaxial growth (SEG) to form oxide isolated silicon device tubs in a sea of field oxide. A thick oxide is grown, or grown and deposited, on a silicon substrate, and openings are formed in the oxide to the silicon substrate. Epitaxial silicon is grown in the openings to form oxide isolated tubs of single crystal silicon. Close spacing of the isolated SEG tubs eliminates the waste area characteristic of the LOCOS bird""s beak, and can provide reduced surface area as compared with the area required for the etched grooves in trench isolation. Consequently, SEG isolation processes allow for higher packing density. They also result in lower device leakage and lower device cost.
SEG isolation is particularly well suited for vertically oriented devices. One of the designs of choice for bipolar devices is a buried collector structure with vertical current flow. Vertical DMOS devices are also desirable from the standpoint of reducing device area on the chip.
In integrated circuits using these device types, a large number of device sites, or SEG isolated regions, are produced on a single wafer. Depending on the IC layout, the size of the SEG regions varies, as well as the spacing between them. It has been found that on SEG wafers, the epi layer thickness shows unacceptable variations between SEG regions across the wafer. The regions showing non-uniformity are both within chip sites and across the wafer, i.e. between chip sites. This is due to xe2x80x9cloadingxe2x80x9d effects in the thermodynamics of epitaxial growth.
We have developed a process for making SEG isolated devices which largely eliminates the non-uniformity in thickness between SEG regions. The process is cost effective and fully compatible with standard processing for making, e.g., vertical complementary bipolar devices with buried collectors. The process is also compatible with making complementary IGBT devices and standard CMOS devices in the same chip. The process eliminates undesirable loading factors through the use of a sea of passive SEG islands surrounding the device sites. This produces uniform growth conditions and uniform growth over the entire wafer, while still retaining isolation between device sites.